Commercialization history
In late 2016,
TSMC announced plans to construct a 5 nm–3 nm node
semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion.
[11]
In 2017, TSMC announced it was to begin construction of the 3 nm
semiconductor fabrication plant at the
Tainan Science Park in Taiwan.
[12] TSMC plans to start volume production of the 3 nm process node in 2023.
[13][14][15][16][17]
In early 2018,
IMEC and
Cadence stated they had taped out 3 nm test chips, using
extreme ultraviolet lithography (EUV) and 193 nm
immersion lithography.
[18]
In early 2019,
Samsung presented plans to manufacture 3 nm
GAAFET (
gate-all-around field-effect transistors) at the 3 nm node in 2021, using its own MBCFET transistor structure that uses nanosheets instead of nanowires; delivering a 35% performance increase, 50% power reduction and a 45% reduction in area when compared with 7nm.
[19][20][21] Samsung's semiconductor roadmap also included products at 8, 7, 6, 5, and 4 nm 'nodes'.
[22][23]
In December 2019, Intel announced plans for 3 nm production in 2025.
[24]
In January 2020, Samsung announced the production of the world's first 3 nm GAAFET process prototype, and said that it is targeting mass production in 2021.
[25]
In August 2020, TSMC announced details of its N3 3nm process, which is new rather than being an improvement over its N5 5nm process.
[26] Compared with the N5 process, the N3 process should offer a 10-15% (1.10-1.15x) increase in performance, or a 25-35% (1.25-1.35x) decrease in power consumption, with a 1.7x increase in logic density (a scaling factor of 0.58x), a 1.2x increase (0.8x scaling factor) in SRAM cell density, and a 1.1x increase in analog circuitry density. Since many designs include considerably more SRAM than logic, (a common ratio being 70% SRAM to 30% logic) die shrinks are expected to only be of around 26%. TSMC plans risk production in 2021 with volume production in the second half of 2022.
[27][28][2]